US 11,940,914 B2
Performance aware partial cache collapse
Hithesh Hassan Lepaksha, Hyderabad (IN); Sharath Kumar Nagilla, Hyderabad (IN); Darshan Kumar Nandanwar, Bangalore (IN); Nirav Narendra Desai, Hyderabad (IN); and Venkata Biswanath Devarasetty, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 27, 2022, as Appl. No. 17/827,302.
Prior Publication US 2023/0401152 A1, Dec. 14, 2023
Int. Cl. G06F 12/08 (2016.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/468 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A method for performing a partial cache collapse procedure, comprising:
counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways;
selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria, wherein selecting the at least one cache way comprises one or more of:
selecting, for collapse, one cache way having a highest number of cache lines that satisfy the eviction criteria, or
selecting multiple cache ways having highest numbers of cache lines that satisfy the eviction criteria; and
performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.