US 11,940,891 B2
Low latency fault and status indicator in serial communication
Scott Allen Monroe, Frisco, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Jul. 29, 2021, as Appl. No. 17/388,858.
Prior Publication US 2023/0031600 A1, Feb. 2, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/3027 (2013.01) [G06F 11/0772 (2013.01); G06F 11/0784 (2013.01); G06F 13/4282 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a serial output communication terminal providing a serial communication; and
an interface circuit communicably connected to the serial output communication terminal and adapted to send an output serial data frame to a controller via the serial output communication terminal, wherein each output serial data frame includes a status phase and a data phase serially followed by at least one cyclic redundancy check (CRC) bit, which is serially followed by a fault bit, in which the fault bit indicates whether a fault is detected during sending of the output serial data frame, the fault bit is followed by a redundancy bit providing a redundant indication of whether a fault is detected, and the interface circuit includes:
control logic;
an input register;
a fault flag register; and
an output register.