US 11,940,888 B2
Technology to provide fault tolerance for elliptic curve digital signature algorithm engines
Santosh Ghosh, Hillsboro, OR (US); Marcio Juliato, Portland, OR (US); and Manoj R. Sastry, Portland, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 14, 2021, as Appl. No. 17/447,600.
Application 17/447,600 is a continuation of application No. 16/199,383, filed on Nov. 26, 2018, granted, now 11,151,007.
Prior Publication US 2022/0083439 A1, Mar. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/27 (2006.01); G06F 11/22 (2006.01); H04L 9/00 (2022.01); H04L 9/30 (2006.01); H04L 9/32 (2006.01)
CPC G06F 11/27 (2013.01) [G06F 11/2236 (2013.01); H04L 9/004 (2013.01); H04L 9/3066 (2013.01); H04L 9/3252 (2013.01); H04L 2209/84 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising:
processor circuitry coupled to memory, the processor circuitry to detect and tolerate faults, the processor circuitry to:
facilitate a self-test unit circuitry to periodically test a fault-tolerant engine circuitry associated with multiple verification state machines (VSMs) to verify digital signatures;
facilitate a signing state machine (SSM) to generate a digital signature of the digital signatures; and
in response to generation of the digital signature, automatically trigger the VSMs to verify the digital signature.