US 11,940,830 B2
Low dropout regulator and memory device including the same
Jinook Jung, Suwon-si (KR); Jaewoo Park, Yongin-si (KR); Junhan Choi, Suwon-si (KR); Myoungbo Kwak, Seoul (KR); and Junghwan Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 31, 2022, as Appl. No. 17/709,853.
Claims priority of application No. 10-2021-0103589 (KR), filed on Aug. 6, 2021.
Prior Publication US 2023/0045744 A1, Feb. 9, 2023
Int. Cl. G11C 11/4074 (2006.01); G05F 1/575 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01)
CPC G05F 1/575 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A low dropout (LDO) regulator, comprising:
a first resistor;
a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node;
an operational amplifier including input terminals respectively connected with a reference voltage and the first node, and an output terminal;
a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node;
a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node; and
a current source connected between the second node and a ground voltage terminal.