US 11,940,271 B2
High power device fault localization via die surface contouring
David J. Lewison, LaGrangeville, NY (US); Jay A. Bunt, Esopus, NY (US); Frank L. Pompeo, Redding, CT (US); Richard Walter Oldrey, Clintondale, NY (US); John D. Sylvestri, Poughkeepsie, NY (US); and Phong T. Tran, Highland, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 17, 2020, as Appl. No. 16/950,855.
Prior Publication US 2022/0155049 A1, May 19, 2022
Int. Cl. G01B 5/20 (2006.01); G01B 5/06 (2006.01); G01B 5/30 (2006.01); H01L 21/67 (2006.01)
CPC G01B 5/20 (2013.01) [G01B 5/06 (2013.01); G01B 5/30 (2013.01); H01L 21/67253 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of preparing a computer processor die, the method comprising:
determining a first warpage shape of the computer processor die at a testing temperature; and
contouring, selectively, a thickness of the computer processor die at a contouring temperature by physically removing material from a surface of the computer processor die such that the surface will be substantially flat at the testing temperature;
wherein the contouring temperature is room temperature.