US 11,938,562 B2
Systems and methods for laser dicing of bonded structures
Feiyan Wang, Wuhan (CN); Xianbin Wang, Wuhan (CN); and Yongwei Li, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Sep. 28, 2021, as Appl. No. 17/488,284.
Application 17/488,284 is a division of application No. 16/543,228, filed on Aug. 16, 2019, granted, now 11,529,700.
Application 16/543,228 is a continuation of application No. PCT/CN2019/092014, filed on Jun. 20, 2019.
Prior Publication US 2022/0016728 A1, Jan. 20, 2022
Int. Cl. B23K 26/0622 (2014.01); B23K 26/035 (2014.01); B23K 26/082 (2014.01); B23K 26/36 (2014.01)
CPC B23K 26/0624 (2015.10) [B23K 26/035 (2015.10); B23K 26/082 (2015.10); B23K 26/36 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for dicing a bonded structure, comprising:
thinning a top surface and a bottom surface of a bonded structure, the bonded structure having a first wafer and a second wafer bonded with a bonding interface;
forming a series of ablation structures in the first wafer and the second wafer, the series of ablation structures between a first part and a second part of the bonded structure; and
separating the first part and the second part of the bonded structure along the series of ablation structures, comprising performing one of:
separating, along a first ablation spot and a second ablation spot vertically aligned with the first ablation spot, the first part and the second part, wherein:
the second part comprises a first device portion located in the first wafer and a second device portion located in the second wafer and bonded with the first device portion by the bonding interface, one of the first device portion and the second device portion comprising one or more semiconductor circuits, and the one or more semiconductor circuits comprising one of a memory array and a peripheral circuit; and
the first part comprises a third device portion located in the first wafer and a fourth device portion located in the second wafer and bonded with the third device portion by the bonding interface, one of the third device portion and the fourth device portion comprising a memory array or a peripheral circuit; and
separating the first part and the second part along a vertical ablation stripe, the vertical ablation stripe penetrating the bonding interface and extending from the first wafer to the second wafer.