| CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H01L 2924/0002 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02)] | 33 Claims |
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[ 23. A three-dimensional (3D) semiconductor device, comprising:
a plurality of gate layers vertically stacked on a substrate and parallel to each other to form a memory stack extending along a first direction, the memory stack having a first width across the first direction;
a plurality of selection lines disposed over the memory stack and parallel to each other, the plurality of selection lines including a first selection line above the memory stack and within the first width of the memory stack, and a second selection line above the memory stack and within the first width of the memory stack, the first and second selection lines are disposed laterally apart from each other and located at same horizontal level;
a plurality of bit lines disposed over the first and second selection lines, arranged in parallel to each other and perpendicular to the first and second selection lines;
a plurality of strings formed vertically to the gate layers and the first and second selection lines, and the strings electrically connected to the corresponding first and second selection lines and electrically connected to the gate layers;
a plurality of cells respectively defined by the strings, the first and second selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns according to the first direction and a second direction, wherein the bit lines are parallel to the second direction while the selection lines are parallel to the first direction; and
a plurality of string contacts formed vertically to the gate layers and the selection lines, and each of the string contacts disposed correspondingly at each of the strings of the cells, wherein the string contacts are electrically connected to the corresponding first selection line, second selection line, and the corresponding bit lines;
wherein adjacent cells in the same column within the first selection line are electrically connected to different bit lines, and adjacent cells in the same column within the second selection line are electrically connected to different bit lines; and
wherein positions of the string contacts are correspondingly shifted away from centers of the strings of the cells.]
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