US 12,262,645 B2
Magnetoresistive random access memory with metal oxide layer on top surface and sidewall of MTJ
An-Chi Liu, Tainan (TW); and Chun-Hsien Lin, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/224,066.
Application 18/224,066 is a continuation of application No. 17/209,251, filed on Mar. 23, 2021, granted, now 11,758,824.
Application 17/209,251 is a continuation of application No. 16/455,674, filed on Jun. 27, 2019, granted, now 10,991,875, issued on Apr. 27, 2021.
Claims priority of application No. 201910467483.9 (CN), filed on May 31, 2019.
Prior Publication US 2023/0363286 A1, Nov. 9, 2023
Int. Cl. H10N 50/80 (2023.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/85 (2023.01)
CPC H10N 50/80 (2023.02) [G11C 11/161 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/85 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate having a magnetic tunneling junction (MTJ) region and a logic region;
a MTJ on the MTJ region;
a metal oxide layer on and directly contacting a top surface and a sidewall of the MTJ; and
a first inter-metal dielectric (IMD) layer on the substrate and around the MTJ, wherein top surfaces of first IMD layer and the metal oxide layer are coplanar.