US 12,262,597 B2
Display substrate and display device
Ying Han, Beijing (CN); Pan Xu, Beijing (CN); Xing Zhang, Beijing (CN); Guangshuang Lv, Beijing (CN); Donghui Zhao, Beijing (CN); Chengyuan Luo, Beijing (CN); and Cheng Xu, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/282,106
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Nov. 28, 2022, PCT No. PCT/CN2022/134711
§ 371(c)(1), (2) Date Sep. 14, 2023,
PCT Pub. No. WO2024/113102, PCT Pub. Date Jun. 6, 2024.
Prior Publication US 2025/0031531 A1, Jan. 23, 2025
Int. Cl. H10K 59/124 (2023.01); G09G 3/00 (2006.01); G09G 3/3225 (2016.01); H10K 59/122 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/124 (2023.02) [G09G 3/3225 (2013.01); H10K 59/122 (2023.02); H10K 59/131 (2023.02); G09G 3/003 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2320/0233 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a base substrate,
a pixel driving circuit layer, on the base substrate and comprising a plurality of pixel driving circuits,
a first planarization layer, on a side of the pixel driving circuit layer away from the base substrate, and comprising a plurality of first vias respectively exposing output terminals of the plurality of pixel driving circuits,
a first metal layer, on a side of the first planarization layer away from the base substrate, and comprising a plurality of data lines extending in a first direction and a plurality of connection electrodes, wherein the plurality of connection electrodes are electrically connected with the output terminals of the plurality of pixel driving circuits through the first vias respectively,
a second planarization layer, on a side of the first metal layer away from the base substrate and comprising a plurality of second vias exposing the plurality of connection electrodes,
a plurality of first electrodes, on a side of the second planarization layer away from the base substrate, and electrically connected with the plurality of connection electrodes through the plurality of second vias respectively, and
a pixel definition layer, on a side of the plurality of first electrodes away from the base substrate and comprising a plurality of first definition walls extending in the first direction and a plurality of second definition walls extending in a second direction, wherein the plurality of first definition walls and the plurality of second definition walls define a plurality of pixel openings, and the first direction is different from the second direction,
wherein an orthographic projection of at least part of the plurality of data lines on the base substrate respectively at least partially overlaps with orthographic projections of the plurality of first definition walls on the base substrate.