US 12,262,560 B2
Integrated circuit devices including transistor stacks having different threshold voltages and methods of forming the same
Jeonghyuk Yim, Halfmoon, NY (US); Ki-Il Kim, Clifton Park, NY (US); Gil Hwan Son, Clifton Park, NY (US); and Kang Ill Seo, Springfield, VA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 29, 2024, as Appl. No. 18/425,476.
Application 18/425,476 is a division of application No. 17/387,178, filed on Jul. 28, 2021, granted, now 11,923,365.
Claims priority of provisional application 63/190,857, filed on May 20, 2021.
Prior Publication US 2024/0170486 A1, May 23, 2024
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/856 (2025.01) [H10D 30/031 (2025.01); H10D 30/6733 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/01 (2025.01); H10D 64/516 (2025.01); H10D 64/518 (2025.01); H10D 84/0179 (2025.01); H10D 84/0181 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit device, the method comprising:
forming a first preliminary complementary field effect transistor (CFET) stack and a second preliminary CFET stack in an insulating layer on a substrate,
wherein the first preliminary CFET stack is in a first opening of the insulating layer and comprises a first upper active region, a first upper gate insulator, a first lower active region, a first lower gate insulator that comprises first dipole elements, and
the second preliminary CFET stack is in a second opening of the insulating layer and comprises a second upper active region, a second upper gate insulator, a second lower active region, and a second lower gate insulator that comprises second dipole elements;
forming a first lower gate work function layer and a first lower gate metal layer on the first lower gate insulator in a lower portion of the first opening and forming a second lower gate work function layer and a second lower gate metal layer on the second lower gate insulator in a lower portion of the second opening, wherein the first lower gate work function layer and the second lower gate work function layer have the same thickness and are formed of the same material; and
forming a first upper gate work function layer and a first upper gate metal layer on the first upper gate insulator in an upper portion of the first opening and forming a second upper gate work function layer and a second upper gate metal layer on the second upper gate insulator in an upper portion of the second opening.