| CPC H10D 84/856 (2025.01) [H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/0259 (2013.01); H01L 21/30604 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/0167 (2025.01); H10D 84/038 (2025.01)] | 13 Claims |

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1. A method of forming a semiconductor device, the method comprising:
forming a vertically stacked superlattice structure on a substrate by
forming a first horizontal gate-all-around (hGAA) structure on a substrate;
forming a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and
forming a second horizontal gate-all-around (hGAA) structure on a top surface of the sacrificial layer,
wherein each of the first hGAA structure and the second hGAA structure comprise alternating layers of nanosheet channel layer and nanosheet release layer, each nanosheet channel layer independently comprising silicon (Si) and each nanosheet release layer independently comprising silicon germanium (SiGe) doped with a dopant, and wherein each nanosheet release layer has an etch rate that is reduced compared to the sacrificial layer.
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