US 12,262,557 B2
Methods and systems to improve uniformity in power FET arrays
Clifford Drowley, Santa Clara, CA (US); Andrew P. Edwards, Santa Clara, CA (US); Hao Cui, Santa Clara, CA (US); and Subhash Srinivas Pidaparthi, Santa Clara, CA (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Mar. 29, 2022, as Appl. No. 17/707,839.
Claims priority of provisional application 63/172,545, filed on Apr. 8, 2021.
Prior Publication US 2022/0328476 A1, Oct. 13, 2022
Int. Cl. H10D 84/83 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/05 (2025.01)
CPC H10D 84/834 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 64/01 (2025.01); H10D 64/512 (2025.01); H10D 84/05 (2025.01); H10D 30/6735 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A vertical, fin-based field effect transistor (FinFET) device comprising:
an array of individual FinFET cells, the array comprising a plurality of rows and columns of separated fins, wherein each of the separated fins is in electrical communication with a source contact;
one or more rows of first inactive fins disposed on a first set of sides of the array of individual FinFET cells;
one or more columns of second inactive fins disposed on a second set of sides of the array of individual FinFET cells; and
a gate region surrounding the individual FinFET cells of the array of individual FinFET cells, the first inactive fins, and the second inactive fins.