| CPC H10D 62/115 (2025.01) [H01L 21/02008 (2013.01); H10D 64/691 (2025.01)] | 18 Claims |

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1. A method of manufacturing a semiconductor structure, comprising:
providing a first semiconductor wafer, wherein the first semiconductor wafer comprises a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance, wherein providing the first semiconductor wafer comprises:
recessing the first top metallization structure to fall below the top surface of the first dielectric layer;
providing a second semiconductor wafer, wherein the second semiconductor wafer comprises a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface of the second dielectric layer by a second distance; and
hybrid-bonding the first semiconductor wafer and the second semiconductor wafer,
wherein providing the first semiconductor wafer further comprises forming an etch stop layer vertically on the second dielectric layer, wherein a thickness of the etch stop layer is substantially equal to the second distance.
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