| CPC H10B 53/30 (2023.02) [H01L 28/55 (2013.01); H01L 28/60 (2013.01); H01L 28/65 (2013.01); H01L 28/75 (2013.01)] | 20 Claims |

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1. A device structure comprising:
a plurality of memory devices laterally spaced apart, wherein individual ones of the plurality of memory devices comprise:
a first conductive layer comprising a first non-Pb based perovskite metal oxide, the first conductive layer comprising a first sidewall having a first slope;
a dielectric layer comprising a non-Pb based perovskite material on the first conductive layer, the dielectric layer comprising a second sidewall having a second slope; and
a second conductive layer comprising a second non-Pb based perovskite metal oxide on the dielectric layer, the second conductive layer comprising a third sidewall having a third slope, wherein the first slope, the second slope, and the third slope are measured relative to a normal to a lowermost surface of the first conductive layer, wherein the first slope comprises a first angle, the second slope comprises a second angle and the third slope comprises a third angle, wherein the third angle is less than the second angle, and wherein the second angle is less than the first angle, and wherein the first slope, the second slope, and the third slope are each greater than or equal to zero degrees.
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