US 12,262,542 B2
Ferroelectric memory device
Han-Jong Chia, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 23, 2023, as Appl. No. 18/357,153.
Application 18/357,153 is a continuation of application No. 16/885,303, filed on May 28, 2020, granted, now 11,758,737.
Prior Publication US 2023/0371274 A1, Nov. 16, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 21/28 (2006.01); H01L 21/3115 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 49/02 (2006.01); H10B 51/30 (2023.01); H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) [H01L 21/3115 (2013.01); H01L 28/60 (2013.01); H01L 29/40111 (2019.08); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A ferroelectric memory device, comprising:
a substrate comprising a first conductive region;
a dielectric layer disposed on the substrate;
a ferroelectric structure comprising stacked ferroelectric layers, the ferroelectric structure comprising a bottom portion and sidewall portions connected to the bottom portion;
a second conductive region disposed on the ferroelectric structure, wherein the second conductive region and the ferroelectric structure are embedded in the dielectric layer, and the second conductive region is laterally spaced apart from the dielectric layer by the sidewall portions of the ferroelectric structure.