| CPC H10B 43/27 (2023.02) [G11C 16/0483 (2013.01); G11C 16/14 (2013.01); H01L 21/31116 (2013.01); H01L 23/528 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H01L 21/0276 (2013.01); H01L 21/31144 (2013.01)] | 19 Claims |

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1. A memory device, comprising:
a bottom select gate (BSG);
a word line positioned over the BSG with a staircase configuration;
a top select gate (TSG) positioned over the word line;
an insulating layer disposed between the BSG, the word line, and the TSG;
a first dielectric trench formed in the BSG and separate the BSG into a plurality of sub-BSGs; and
a second dielectric trench formed in the TSG and separating the TSG into a plurality of sub-TSGs; wherein:
the first dielectric trench and the second dielectric trench are aligned with each other in a height direction of the insulating layer and are spaced apart by the word line.
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