US 12,262,538 B2
Semiconductor device and manufacturing method of the semiconductor device
Jae Hyoung Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Sep. 11, 2023, as Appl. No. 18/464,828.
Application 18/464,828 is a continuation of application No. 17/073,835, filed on Oct. 19, 2020, granted, now 11,778,822.
Claims priority of application No. 10-2020-0058496 (KR), filed on May 15, 2020.
Prior Publication US 2023/0422507 A1, Dec. 28, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 63/34 (2023.02); H10B 63/845 (2023.02); H10N 70/066 (2023.02); H10N 70/231 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an insulating structure;
a source structure and a first insulating layer on the insulating structure;
a first contact penetrating the source structure;
a second contact passing through the first insulating layer;
a first stack on the source structure and the first insulating layer;
a third contact passing through the first stack and coupled to the second contact;
a second stack on the first stack;
a fourth contact passing through the second stack and coupled to the third contact;
a channel structure passing through the first and second stacks; and
a memory layer enclosing the channel structure,
wherein the memory layer comprises:
a first memory part passing through the second stack, a second memory part passing through the first stack, and a third memory part coupling the first memory part and the second memory part, and
wherein a level of an upper surface of the third memory part is the same as a level of a boundary between the third and fourth contacts.