US 12,262,537 B2
Vertical type semiconductor devices and methods of manufacturing the same
Eun-Taek Jung, Seongnam-si (KR); Joong-Shik Shin, Yongin-si (KR); and Byung-Kwan You, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 23, 2024, as Appl. No. 18/419,818.
Application 18/419,818 is a continuation of application No. 17/654,779, filed on Mar. 14, 2022, granted, now 11,968,835.
Application 17/654,779 is a continuation of application No. 16/933,328, filed on Jul. 20, 2020, granted, now 11,276,709, issued on Mar. 5, 2022.
Application 16/933,328 is a continuation of application No. 16/115,246, filed on Aug. 28, 2018, granted, now 10,741,575, issued on Aug. 11, 2020.
Claims priority of application No. 10-2017-0150741 (KR), filed on Nov. 13, 2017.
Prior Publication US 2024/0172441 A1, May 23, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H10B 41/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/31111 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01); H10B 41/27 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a vertical type semiconductor device, comprising:
forming a first pattern structure on a substrate;
forming a second pattern that passes through the first pattern structure and the substrate;
depositing alternately and repeatedly insulation layers and sacrificial layers on the first pattern structure and the second pattern so that a first stacked structure is formed;
forming a preliminary channel structure that includes a blocking layer, a charge storage layer, a tunnel insulation layer and a channel layer, wherein the preliminary channel structure passes through the first stacked structure and the first pattern structure and extends to an upper portion of the second pattern;
etching portions of the first stacked structure and the first pattern structure so that a trench that extends a first direction parallel to a surface of the substrate is formed;
removing the first pattern structure exposed by the trench so that a first gap is formed;
etching portions of the blocking layer, the charge storage layer, and the tunnel insulation layer exposed by the first gap so that a channel structure that has a cutting region is formed;
forming a semiconductor layer that fills the first gap and the cutting region, wherein the semiconductor layer contacts the channel layer in the cutting region; and
replacing the sacrificial layers with first conductive patterns.