US 12,262,536 B2
Arrays of memory cells including pairs of memory cells having respective charge storage nodes between respective access lines
Theodore T. Pekny, Sunnyvale, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 25, 2022, as Appl. No. 17/872,158.
Application 13/047,215 is a division of application No. 12/047,414, filed on Mar. 13, 2008, granted, now 7,906,818, issued on Mar. 15, 2011.
Application 17/872,158 is a continuation of application No. 16/736,297, filed on Jan. 7, 2020, granted, now 11,398,493.
Application 16/736,297 is a continuation of application No. 16/545,504, filed on Aug. 20, 2019, granted, now 10,957,709, issued on Mar. 23, 2021.
Application 16/545,504 is a continuation of application No. 15/691,794, filed on Aug. 31, 2017, granted, now 10,522,559, issued on Dec. 31, 2019.
Application 15/691,794 is a continuation of application No. 15/246,847, filed on Aug. 25, 2016, granted, now 9,768,194, issued on Sep. 19, 2017.
Application 15/246,847 is a continuation of application No. 14/820,027, filed on Aug. 6, 2015, granted, now 9,455,266, issued on Sep. 27, 2016.
Application 14/820,027 is a continuation of application No. 13/676,407, filed on Nov. 14, 2012, granted, now 9,147,693, issued on Sep. 29, 2015.
Application 13/676,407 is a continuation of application No. 13/047,215, filed on Mar. 14, 2011, granted, now 8,329,513, issued on Dec. 11, 2012.
Prior Publication US 2022/0359567 A1, Nov. 10, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 29/0649 (2013.01); H01L 29/40117 (2019.08); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02)] 24 Claims
OG exemplary drawing
 
1. An array of memory cells, comprising:
a first memory cell having a control gate connected to a first access line, having a channel, and having a charge storage node between its control gate and its channel, wherein the first access line forms the control gate of the first memory cell;
a second memory cell having a control gate connected to a second access line, having a channel, and having a charge storage node between its control gate and its channel, wherein the second access line forms the control gate of the second memory cell; and
an isolation region between the first access line and the second access line;
wherein the charge storage node of the first memory cell is between the first access line and a first side of the isolation region;
wherein the charge storage node of the second memory cell is between the second access line and a second side of the isolation region opposite the first side of the isolation region;
wherein the charge storage node of the first memory cell has a curved cross-section having a first end in contact with a first portion of the isolation region on the first side of the isolation region, and has a second end in contact with a second portion of the isolation region on the first side of the isolation region; and
wherein the charge storage node of the second memory cell has a curved cross-section having a first end in contact with the first portion of the isolation region on the second side of the isolation region, and has a second end in contact with the second portion of the isolation region on the second side of the isolation region.