US 12,262,534 B2
Semiconductor devices and electronic systems including the same
Wooyong Jeon, Anyang-si (KR); and Moorym Choi, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 8, 2022, as Appl. No. 17/667,156.
Claims priority of application No. 10-2021-0054393 (KR), filed on Apr. 27, 2021.
Prior Publication US 2022/0344361 A1, Oct. 27, 2022
Int. Cl. H10B 41/40 (2023.01); H01L 23/48 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/40 (2023.02) [H01L 23/481 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a peripheral circuit structure including peripheral circuits that are on a semiconductor substrate, and first bonding pads that are electrically connected to the peripheral circuits; and
a cell array structure including a memory cell array including memory cells that are three-dimensionally arranged on a semiconductor layer, and second bonding pads that are electrically connected to the memory cell array and are coupled to the first bonding pads,
wherein the cell array structure comprises:
a resistor pattern positioned at the same level as the semiconductor layer;
a stack including insulating layers and electrodes that are vertically and alternately stacked on the semiconductor layer; and
vertical structures penetrating the stack.