US 12,262,533 B2
Dynamic flash memory (DFM) with multi-cells
Tao Yang, Hubei (CN); Dongxue Zhao, Hubei (CN); Yuancheng Yang, Hubei (CN); Lei Liu, Hubei (CN); Kun Zhang, Hubei (CN); Di Wang, Hubei (CN); Wenxi Zhou, Hubei (CN); Zhiliang Xia, Hubei (CN); and Zongliang Huo, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Apr. 28, 2022, as Appl. No. 17/731,524.
Prior Publication US 2023/0354599 A1, Nov. 2, 2023
Int. Cl. H01L 23/52 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 41/35 (2023.02) [H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A three-dimensional memory device comprising:
a first memory cell comprising:
a first pillar configured to store a first electrical charge;
a first insulating layer surrounding the first pillar;
a first gate contact surrounding a first portion of the first insulating layer, the first gate contact coupled to a first word line configured to address and non-destructively read the first pillar; and
a second gate contact surrounding a second portion of the first insulating layer, the second gate contact coupled to a first plate line configured to program the first pillar;
a second memory cell comprising:
a second pillar configured to store a second electrical charge;
a second insulating layer surrounding the second pillar;
a third gate contact surrounding a first portion of the second insulating layer, the third gate contact coupled to a second word line configured to address and non-destructively read the second pillar; and
a fourth gate contact surrounding a second portion of the second insulating layer, the fourth gate contact coupled to a second plate line configured to program the second pillar;
a control gate between the first and second memory cells and configured to provide a charge isolation region between the first and second memory cells, the control gate comprising:
a recessed pillar;
a recessed insulating layer surrounding the recessed pillar; and
a control gate contact surrounding the recessed insulating layer;
a top contact coupled to the first memory cell, the top contact coupled to a bit line configured to flow electrical charge through the first and second memory cells; and
a bottom contact coupled to the second memory cell, the bottom contact coupled to a source line configured to flow electrical charge through the first and second memory cells,
wherein the first word line is closer to the top contact than the first plate line, the control gate is between the second and fourth gate contacts and the third gate contact is adjacent to the source line.