US 12,262,531 B2
Memory cell structure, memory array structure, semiconductor structure having a capacitor structure surrounded on the outer side of the word line
Guangsu Shao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on May 26, 2022, as Appl. No. 17/824,905.
Application 17/824,905 is a continuation of application No. PCT/CN2022/077731, filed on Feb. 24, 2022.
Claims priority of application No. 202210133620.7 (CN), filed on Feb. 14, 2022.
Prior Publication US 2023/0262964 A1, Aug. 17, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/485 (2023.02) [H10B 12/0387 (2023.02); H10B 12/37 (2023.02); H10B 12/482 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A memory cell structure, comprising:
a substrate having a bit line structure therein;
an active region positioned on the bit line structure, in a direction perpendicular to the substrate, the active region comprising a first connection terminal, a second connection terminal away from the first connection terminal, and a channel region positioned between the first connection terminal and the second connection terminal, the first connection terminal being electrically connected to the bit line structure;
a word line structure, in the direction perpendicular to the substrate, the word line structure covering a sidewall of the channel region;
an insulating dielectric layer covering an outer side of the word line structure, an outer side of the first connection terminal, and an outer side of the second connection terminal; and
a capacitor structure covering an outer side of the insulating dielectric layer, a top surface of the insulating dielectric layer, and a top surface of the second connection terminal, the capacitor structure being electrically connected to the second connection terminal.