US 12,262,530 B2
Semiconductor structure and forming method thereof
Shih-Hung Lee, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Nov. 3, 2021, as Appl. No. 17/453,361.
Application 17/453,361 is a continuation of application No. PCT/CN2021/107436, filed on Jul. 20, 2021.
Claims priority of application No. 202110215088.9 (CN), filed on Feb. 25, 2021.
Prior Publication US 2022/0271039 A1, Aug. 25, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/03 (2023.02); H10B 12/30 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
providing a substrate and a plurality of discrete bit line structures, the bit line structures being located on the substrate, capacitor contact windows being provided between adjacent bit line structures;
forming first isolation layers, the first isolation layers covering sidewalls of the bit line structures;
forming a sacrificial layer, the sacrificial layer covering sidewalls of the first isolation layers;
forming second isolation layers, the second isolation layers covering sidewalls of the sacrificial layer and exposing top surfaces and bottoms of the sacrificial layer;
etching the top surfaces and the bottoms of the sacrificial layer to form top gaps, bottom gaps and a remaining part of the sacrificial layer between the first isolation layers and the second isolation layers; and
etching from the top surfaces of the sacrificial layer to remove the remaining part of the sacrificial layer so as to form gaps directly between the first isolation layers and the second isolation layers.