| CPC H10B 12/34 (2023.02) [H10B 12/053 (2023.02); H10B 12/488 (2023.02)] | 13 Claims |
|
1. A semiconductor device, comprising:
a semiconductor substrate, comprising: shallow trench isolation regions, and multiple active regions that are arranged at intervals and defined by the shallow trench isolation regions;
a word line trench formed on the semiconductor substrate, the word line trench being disposed to intersect with corresponding active regions; wherein the word line trench comprises a first word line trench and a second word line trench; an orthographic projection of the first word line trench on the semiconductor substrate is positioned within an orthographic projection of a respective shallow trench isolation region on the semiconductor substrate; and an orthographic projection of the second word line trench on the semiconductor substrate is positioned within an orthographic projection of a respective active region on the semiconductor substrate; and
a word line structure embedded in the word line trench; wherein the word line structure comprises a first word line structure part and a second word line structure part connected to each other; the first word line structure part is formed in the first word line trench, and the second word line structure part is formed in the second word line trench;
wherein the first word line structure part comprises an avoidance region, a top surface of the avoidance region is aligned with a top surface of the second word line structure part, and the avoidance region is provided with insulating material;
wherein the second word line structure part is a solid structure; a cross section of the first word line structure part comprises a concave region in an extension direction perpendicular to the word line structure; the avoidance region comprises the concave region;
wherein a top surface of the concave region is aligned with a top surface of the second word line structure part in a direction perpendicular to a top surface of the semiconductor substrate;
in the direction perpendicular to the top surface of the semiconductor substrate, a bottom surface of the concave region is higher than a bottom surface of the second word line structure part, and a bottom surface of the first word line structure part is lower than a bottom surface of the second word line structure part;
wherein the word line structure comprises: a gate oxide layer and word lines; wherein the gate oxide layer covers a side wall of the word line trench; and the gate oxide layer is positioned between the word lines and the word line trench:
a word line in the first word line structure part is a solid structure;
in the first word line structure part, a top surface of the word lines is lower than a top surface of the gate oxide layer; and
in the first word line structure part, a respective word line serves as a bottom of the concave region, and the gate oxide layer disposed on the side wall of the word line trench serves as a side wall of the concave region.
|