US 12,262,528 B2
Manufacturing method of memory structure
Keng-Ping Lin, Taichung (TW); Shu-Ming Li, Taichung (TW); and Tzu-Ming Ou Yang, Taichung (TW)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Oct. 26, 2022, as Appl. No. 17/973,558.
Application 17/973,558 is a division of application No. 17/306,874, filed on May 3, 2021, granted, now 11,527,537.
Prior Publication US 2023/0049425 A1, Feb. 16, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/485 (2023.02); H10B 12/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A manufacturing method of a memory structure, comprising:
providing a substrate, wherein the substrate comprises a memory array region;
forming a bit line structure in the memory array region, wherein the bit line structure is located on the substrate;
forming a contact structure in the memory array region, wherein the contact structure is located on the substrate on one side of the bit line structure;
forming a stop layer in the memory array region, wherein the stop layer is located above the bit line structure;
forming a capacitor structure in the memory array region, wherein
the capacitor structure passes through the stop layer and is electrically connected to the contact structure, and
a bottom surface of the capacitor structure is lower than a bottom surface of the stop layer; and
forming the stop layer in the memory array region and the peripheral circuit region, wherein a top surface of the stop layer located in the memory array region is higher than a top surface of the stop layer located in the peripheral circuit region.