US 12,262,527 B2
Vertical-channel cell array transistor structure and dram device including the same
Changseok Lee, Gwacheon-si (KR); Sangwon Kim, Seoul (KR); Changhyun Kim, Seoul (KR); Kyung-Eun Byun, Seongnam-si (KR); and Eunkyu Lee, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 9, 2022, as Appl. No. 17/668,004.
Claims priority of application No. 10-2021-0119860 (KR), filed on Sep. 8, 2021.
Prior Publication US 2023/0072229 A1, Mar. 9, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/24 (2006.01); H01L 29/76 (2006.01); H01L 29/786 (2006.01)
CPC H10B 12/315 (2023.02) [H01L 29/1606 (2013.01); H01L 29/2003 (2013.01); H01L 29/24 (2013.01); H01L 29/7606 (2013.01); H01L 29/78642 (2013.01); H10B 12/488 (2023.02); H10B 12/02 (2023.02); H10B 12/033 (2023.02); H10B 12/30 (2023.02)] 27 Claims
OG exemplary drawing
 
1. A vertical-channel cell array transistor structure comprising:
a semiconductor substrate;
a plurality of channels arranged in an array on the semiconductor substrate, each of the plurality of channels extending perpendicularly from the semiconductor substrate;
a gate insulating layer on the plurality of channels;
a plurality of word lines on the semiconductor substrate and extending in a first direction; and
a two-dimensional (2D) material layer directly contacting at least one surface of each of the plurality of word lines.