US 12,262,524 B2
Method of manufacturing memory device having word lines with improved resistance
Jung-Yu Wu, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Dec. 20, 2021, as Appl. No. 17/555,758.
Prior Publication US 2023/0200046 A1, Jun. 22, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/09 (2023.02) [H10B 12/053 (2023.02); H10B 12/34 (2023.02); H10B 12/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a memory device, comprising:
providing a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region;
forming a first recess extending into the semiconductor substrate from a top surface thereof and disposed in the array region;
forming a word line disposed within the first recess, wherein the word line has a protruding portion protruded out of the top surface of the semiconductor substrate; and
forming a dielectric layer on the top surface of the semiconductor substrate, wherein the protruding portion of the word line is surrounded by the dielectric layer;
wherein the formation of the word line includes disposing an insulating layer conformal to the first recess at a position that a top surface of the insulating layer is coplanar with the top surface of the semiconductor substrate, and forming a conductive member surrounded by the insulating layer and having a second recess extending into the conductive member and toward the semiconductor substrate, wherein the protruding portion of the word line is defined at an upper portion of the conductive member;
wherein the conductive member has a bottom end disposed at a bottom portion of the first recess and a top surface which is extended above the top surface of the semiconductor substrate and is coplanar with a top surface of the dielectric layer.