US 12,262,523 B2
Manufacturing method of semiconductor structure and semiconductor structure
Deyuan Xiao, Hefei (CN); Yong Yu, Hefei (CN); and Guangsu Shao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed on Aug. 9, 2022, as Appl. No. 17/818,537.
Application 17/818,537 is a continuation of application No. PCT/CN2022/077681, filed on Feb. 24, 2022.
Claims priority of application No. 202111444518.0 (CN), filed on Nov. 30, 2021.
Prior Publication US 2023/0171939 A1, Jun. 1, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/0383 (2023.02) [H10B 12/482 (2023.02); H10B 12/488 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate;
forming a plurality of silicon pillars on the substrate, wherein the silicon pillars are arranged as an array;
preprocessing the silicon pillar to form an active pillar, wherein along a first direction, the active pillar comprises a first segment, a second segment, and a third segment that are sequentially connected;
forming a first gate oxide layer on sidewalls of the second segment and the third segment; and
forming a second gate oxide layer on the first gate oxide layer, wherein along the first direction, a length of the second gate oxide layer is less than that of the first gate oxide layer, a top surface of the second gate oxide layer is flush with that of the third segment, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.