US 12,262,521 B2
Manufacturing method of semiconductor memory device
Nam Jae Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Sep. 5, 2023, as Appl. No. 18/461,291.
Application 18/461,291 is a continuation of application No. 17/527,888, filed on Nov. 16, 2021, granted, now 11,751,376.
Application 17/527,888 is a continuation of application No. 16/932,304, filed on Jul. 17, 2020, granted, now 11,205,653, issued on Dec. 21, 2021.
Claims priority of application No. 10-2020-0011962 (KR), filed on Jan. 31, 2020.
Prior Publication US 2023/0413506 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/88 (2006.01); H10B 10/00 (2023.01)
CPC H10B 10/18 (2023.02) 8 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a base part;
sequentially forming, over the base part, a first etch stop layer, a source sacrificial layer, and a second etch stop layer;
forming a stack structure, including insulating patterns and sacrificial patterns, over the second etch stop layer;
forming a channel structure that penetrates the stack structure, the second etch stop layer, the source sacrificial layer, and the first etch stop layer, wherein a portion of the channel structure is disposed in a portion of the base part;
forming a trench that penetrates the stack structure and the second etch stop layer, wherein sides of the insulating patterns and the sacrificial patterns are exposed through the trench;
removing the sacrificial patterns between the insulating patterns;
forming conductive patterns between the insulating patterns;
removing the source sacrificial layer; and
forming a source layer between the first and second etch stop layers.