| CPC H04W 72/25 (2023.01) [H04L 1/0057 (2013.01); H04L 1/0067 (2013.01); H04L 1/0071 (2013.01); H04L 1/1854 (2013.01)] | 20 Claims |

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1. A baseband processor configured to, when executing instructions stored in a memory, perform operations comprising:
receiving downlink control information from a base station indicating timing for transmission of sidelink hybrid automatic repeat request (HARQ) feedback to the base station;
determining that the indicated timing for transmitting the sidelink HARQ feedback overlaps, at least in part, with a second transmission, wherein the second transmission comprises an uplink message;
determining, in response to determining that the indicated timing for transmitting the sidelink HARQ feedback overlaps with the second transmission, a priority of the sidelink HARQ feedback; and
based at least on a comparison of the priority of the sidelink HARQ feedback to a threshold,
when sidelink data associated with the sidelink HARQ feedback does not have a same priority class as the second transmission, sending either the sidelink HARQ feedback or the second transmission to an interface with radio frequency (RF) circuitry for transmission to the base station, or
when the sidelink data associated with the sidelink HARQ feedback has the same priority class as the second transmission, sending the second transmission piggybacked with the sidelink HARQ feedback to the interface with the RF circuitry for transmission to the base station.
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