| CPC H04W 72/23 (2023.01) [H04L 5/0053 (2013.01); H04W 84/042 (2013.01); H04W 88/08 (2013.01)] | 20 Claims |

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1. A baseband processor of a base station, comprising:
a memory; and
a processor coupled to the memory, wherein the processor is configured to execute instructions stored in the memory to cause the base station to:
transmit, to a user equipment (UE), a control signal on a physical downlink control channel (PDCCH) including scheduling information for a data signal on a physical downlink shared channel (PDSCH);
determine one or more demodulation reference signal (DMRS) symbols based on a number of symbols occupied by the PDSCH, a position of the symbols occupied by the PDSCH, and a position of symbols occupied by the PDCCH; and
transmit, to the UE, a DMRS during the one or more determined DMRS symbols.
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