US 12,262,134 B2
Solid-state imaging element, imaging device, and method for controlling solid-state imaging element
Hiromu Kato, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 18/259,454
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Dec. 16, 2021, PCT No. PCT/JP2021/046448
§ 371(c)(1), (2) Date Jun. 27, 2023,
PCT Pub. No. WO2022/172586, PCT Pub. Date Aug. 18, 2022.
Claims priority of application No. 2021-020362 (JP), filed on Feb. 12, 2021.
Prior Publication US 2024/0064437 A1, Feb. 22, 2024
Int. Cl. H04N 25/772 (2023.01); H04N 25/767 (2023.01); H04N 25/778 (2023.01)
CPC H04N 25/772 (2023.01) [H04N 25/767 (2023.01); H04N 25/778 (2023.01)] 10 Claims
OG exemplary drawing
 
10. A method for controlling a solid-state imaging element, the method comprising:
a reset level sampling step of causing a first individual capacitor to hold a predetermined first reset level and causing a second individual capacitor to hold a predetermined second reset level; and
a sample-and-hold step of performing correlated double sampling processing of causing a common capacitor and the first individual capacitor to hold a first output level according to a difference between the first reset level and a first signal level according to an exposure amount and causing the common capacitor and the second individual capacitor to hold a second output level according to a difference between the second reset level and a second signal level according to an exposure amount.