CPC H04N 21/2662 (2013.01) [H04N 21/2187 (2013.01); H04N 21/2401 (2013.01); H04N 21/4147 (2013.01)] | 20 Claims |
20. A computing system comprising:
at least one processor; and
at least one memory storing instructions that, when executed by the processor, cause the computing system to perform a process comprising:
determining if a time shift buffer (TSB) is available;
in an event that the TSB is available, enabling the TSB to hold data in a circular fashion;
monitoring a streaming bitrate for a client device during a live streaming process;
notifying, by a buffer switch handler (BSH) module, a media engine to transcode buffered data in a media buffer in a lower bitrate compared to the streaming bitrate;
in response to a change of the streaming bitrate during the live streaming process, notifying the bitrate change to the BSH module;
sending a request to adjust the streaming bitrate for the client device to the media engine; and
switching, based on the request, a media source of the live streaming process.
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