| CPC H04L 9/0631 (2013.01) [G06F 1/26 (2013.01)] | 8 Claims |
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1. An apparatus comprising:
a processor;
memory storing a plaintext, an encryption key, a current state matrix, a resultant state matrix, and a ciphertext;
a first, a second, a third, and a fourth plurality of interconnections; and
a first, a second, a third, a fourth, and a fifth four-by-one multiplexers; wherein
the processor, the memory, the first, second, third, fourth, and fifth four-by-one multiplexers, and the first, second, third, and fourth plurality of interconnections perform an encryption and decryption process comprising using an iterated block cipher to convert the plaintext to the ciphertext using the encryption key by applying a byte substitution operation using a substitution table, a row shifting operation that shifts rows of a state array by different offsets, a column mixing operation that mixes column data of the state array, and a round key adding operation that adds a round key to the current state matrix of each round of a round function,
wherein the byte substitution operation is performed in the same step as the row shifting operation by including a look-up table,
wherein the plaintext is transformed into the current state matrix and the resultant state matrix as intermediate values during intermediate operations of the iterated block cipher, and
wherein the row shifting operation comprises:
using the first plurality of interconnections to connect a first row of the current state matrix to the first four-by-one multiplexer in an order of first row elements, wherein an arrangement of the first plurality of interconnections preserves the order of first row elements of the current state matrix as an order of inputs into the first four-by-one multiplexer;
transmitting from the first four-by-one multiplexer to the fifth four-by-one multiplexer the first row elements of the resultant state matrix, in the order received by the first four-by-one multiplexer;
using the second plurality of interconnections to connect a second row of the current state matrix to the second four-by-one multiplexer, wherein an arrangement of the second plurality of interconnections shifts an order of second row elements of the current state matrix by one to the left for input into the second four-by-one multiplexer;
transmitting from the second four-by-one multiplexer to the fifth four-by-one multiplexer the second row elements of the resultant state matrix, in the order received by the second four-by-one multiplexer;
using the third plurality of interconnections to connect a third row of the current state matrix to the third four-by-one multiplexer, wherein an arrangement of the third plurality of interconnections shifts an order of third row elements of the current state matrix by two to the left for input into the third four-by-one multiplexer;
transmitting from the third four-by-one multiplexer to the fifth four-by-one multiplexer the third row elements of the resultant state matrix, in the order received by the third four-by-one multiplexer;
using the fourth plurality of interconnections to connect a fourth row of the current state matrix to the fourth four-by-one multiplexer, wherein an arrangement of the fourth plurality of interconnections shifts an order of fourth row elements of the current state matrix by three to the left for input into the fourth four-by-one multiplexer;
transmitting from the fourth four-by-one multiplexer to the fifth four-by-one multiplexer the fourth row elements of the resultant state matrix, in the order received by the fourth four-by-one multiplexer; and transmitting from the fifth four-by-one multiplexer to the resultant state matrix each element in a row-by-row fashion, in the order the elements were received by the fifth four-by-one multiplexer.
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