| CPC H04L 7/0016 (2013.01) [H04L 7/0079 (2013.01)] | 18 Claims |
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1. A receiver comprising an integrated circuit having:
an analog to digital converter that samples a receive signal in accordance with a sample clock to provide a sampled receive signal; and
a clock recovery circuit that includes:
a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock in part by:
obtaining a sampling clock phase estimate from each of multiple pairs of the receive signal samples during a preamble period; and
differencing the sampling clock phase estimates to determine the initial frequency offset; and
a feedback loop to minimize timing error of the sample clock after the initial frequency offset and the initial phase offset have been corrected.
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