| CPC H04L 47/22 (2013.01) [H04L 41/145 (2013.01)] | 12 Claims |

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1. An apparatus for protocol independent deterministic transport of data in a time-sensitive network, the apparatus comprising: at least one processor; and at least one memory including instructions which, when executed by the at least one processor, cause the apparatus to: receive synchronization data from the time-sensitive network, the synchronization data comprising a measure for a clock frequency supporting transport of deterministic data traffic over the time-sensitive network; receive multiple input packets, the input packets comprising deterministic data traffic and non-deterministic data traffic; determine timing information comprising information related to at least one of arrival times or departure times for deterministic traffic; and generate, from the multiple input packets and using the synchronization data and the timing information, a set of isochronous output packets comprising respective payloads and headers, the set of isochronous output packets preceded by a protocol-independent packet header.
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