US 12,261,724 B2
SERDES circuit automatic gain control and convergence
Itamar Levin, Holon (IL); and Tali Warshavsky, Ramat Gan (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,205.
Prior Publication US 2023/0100177 A1, Mar. 30, 2023
Int. Cl. H04L 25/03 (2006.01); G06F 13/42 (2006.01); H03G 3/30 (2006.01); H04B 1/16 (2006.01)
CPC H04L 25/03885 (2013.01) [G06F 13/4221 (2013.01); H03G 3/30 (2013.01); H04B 1/16 (2013.01); G06F 2213/0026 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an analog receiver to generate an analog-to-digital converter (ADC) digital signal based on a received analog input signal;
a data path circuit including:
a digitally controlled equalizer to generate a digitally equalized signal based on the ADC digital signal and a plurality of equalizer coefficients; and
a slicer to generate a sliced data stream and a sliced error stream based on the digitally equalized signal; and
a digital signal processing (DSP) circuit to generate a converged data stream output and the plurality of equalizer coefficients based on the sliced data stream and the sliced error stream;
wherein the slicer is further to generate a gain-controlled data stream and a gain-controlled sliced error stream based on a slicer reference level, the slicer reference level generated based on the plurality of equalizer coefficients.