US 12,261,705 B2
Computing device and computing method for computing packet transmission time
Chien-Hsun Liao, HsinChu (TW); and Wei-Hsuan Chang, HsinChu (TW)
Assigned to Realtek Semiconductor Corp., HsinChu (TW)
Filed by Realtek Semiconductor Corp., HsinChu (TW)
Filed on Sep. 26, 2023, as Appl. No. 18/373,268.
Claims priority of application No. 111139462 (TW), filed on Oct. 18, 2022.
Prior Publication US 2024/0137165 A1, Apr. 25, 2024
Int. Cl. H04L 1/20 (2006.01); H03M 13/00 (2006.01); H04L 1/18 (2023.01); H04L 1/1867 (2023.01)
CPC H04L 1/203 (2013.01) [H04L 1/1887 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A computing device for computing a packet transmission time to select a data rate to improve a performance of the computing device, comprising:
a storage circuit, for storing an arbitration interframe space (AIFS) time, at least one expected value of at least one backoff time, a preamble time, a short interframe space (SIFS) time and an acknowledgement (ACK) time;
a first computing circuit, for computing a payload time according to a packet length and a packet rate;
a second computing circuit, coupled to the storage circuit and the first computing circuit, for computing at least one packet transmission time according to the AIFS time, the at least one expected value of the at least one backoff time, the preamble time, the SIFS time, the ACK time and the payload time; and
a third computing circuit, coupled to the second computing circuit, for computing a total packet transmission time according to the at least one packet transmission time and an estimated packet error rate.