| CPC H04L 1/0061 (2013.01) [H04W 28/06 (2013.01); H04W 76/19 (2018.02); H04W 80/02 (2013.01)] | 20 Claims |

|
1. A terminal device, comprising:
a physical layer (PHY) decoding accelerator, a downlink data processing accelerator and a communication processor (CP); wherein:
the PHY decoding accelerator is configured to decode and perform cyclic redundancy check (CRC) on received downlink data, and send each correctly decoded transport block (TB) to the downlink data processing accelerator to trigger the downlink data processing accelerator for data processing;
the downlink data processing accelerator is configured to perform processing operations of a media access control (MAC) layer, a radio link control (RLC) layer, and a packet data convergence protocol (PDCP) layer on the TB, to obtain an MAC control element (CE), an RLC control protocol data unit (PDU), an RLC transparent mode data protocol data unit (TMD PDU), a PDCP control protocol data unit (PDU) and a PDCP data service data unit (SDU); and
the CP is configured to process the MAC CE, the RLC control PDU, the RLC TMD PDU, the PDCP control PDU and the PDCP data SDU.
|