US 12,261,626 B2
Coding circuit and memory device including the same
Minseo Kim, Seoul (KR); Jongsun Park, Seoul (KR); and Jinho Jeong, Icheon (KR)
Assigned to SK hynix Inc., Icheon (KR); and KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, Seoul (KR)
Filed by SK hynix Inc., Icheon (KR); and KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, Seoul (KR)
Filed on Jul. 24, 2023, as Appl. No. 18/357,763.
Claims priority of application No. 10-2023-0029220 (KR), filed on Mar. 6, 2023.
Prior Publication US 2024/0305312 A1, Sep. 12, 2024
Int. Cl. H03M 13/11 (2006.01); H03M 13/15 (2006.01)
CPC H03M 13/1177 (2013.01) [H03M 13/152 (2013.01); H03M 13/158 (2013.01)] 12 Claims
OG exemplary drawing
 
7. A memory device comprising:
a memory cell array; and
a coding circuit configured to provide an input codeword to the memory cell array by encoding input data, and to generate output data and a detection signal by decoding an output codeword output from the memory cell array,
wherein the coding circuit includes:
an encoder circuit configured to generate the input codeword by concatenating the input data and a parity generated by processing the input data using an odd parity generator matrix; and
a decoder circuit configured to correct a double error from the output codeword, and to detect a triple error using a syndrome generated by processing the output codeword using the odd parity generator matrix,
wherein each column of the odd parity generator matrix has a respective odd number of 1's, and
wherein the odd parity generator matrix corresponds to a plurality of columns selected from a generator matrix corresponding to a predetermined generator function for Bose-Chauduri-Hocquenghem (BCH) coding on a finite field GF (2m), each selected column having a respective odd number of 1's.