US 12,261,625 B2
Single error correct double error detect (SECDED) error coding with burst error detection capability
Michael Thomas Imel, Beaverton, OR (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Dec. 10, 2021, as Appl. No. 17/548,176.
Claims priority of provisional application 63/158,291, filed on Mar. 8, 2021.
Claims priority of provisional application 63/125,311, filed on Dec. 14, 2020.
Prior Publication US 2022/0190846 A1, Jun. 16, 2022
Int. Cl. H03M 13/11 (2006.01); H03M 13/19 (2006.01)
CPC H03M 13/1174 (2013.01) [H03M 13/19 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
an error encoder to receive a data word of k bits from a sequester circuit and to encode the data word using circuitry representing a G-matrix to generate an encoded word of n bits, the n bits including the k bits and a-k check bits, wherein the circuitry representing the G-matrix is based on circuitry representing a parity check matrix, the circuitry representing the parity check matrix to define a single error correct, double error detect, and burst error detect (SECDEDBED) code;
transmit circuitry to transmit the encoded data word to a second IC device;
an error decoder to receive the encoded word from the second IC device as a received encoded word and to apply the circuitry representing the parity check matrix to the encoded word, the circuitry representing the parity check matrix configured to generate a received data syndrome from the received encoded word, the received data syndrome used in a comparison process that compares the received data syndrome to a transmitted data syndrome, the comparison process to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the data word of k bits, wherein m<n−k;
transfer circuitry to transfer the decoded data word to the requestor circuit; and
wherein the circuitry representing the parity check matrix is configured to constrain all possible unique syndrome codes for coding the data word to a reduced-set of candidate syndrome codes that are determined during a semiconductor fabrication process via a search method, the search method comprising:
generating a set of unique odd bit set syndrome codes comprising bit set weighting values from 3 to (n−k)/2−1;
selecting k syndrome codes from the set;
generating burst error syndromes of between 2 and m bits within a boundary of m adjacent bits; and
determining failing burst error syndromes and replacing the failing burst error syndromes with replacement syndromes until a burst error detection probability reaches a predetermined threshold.