US 12,261,624 B2
Error correction coding apparatus and error correction decoding apparatus
Hideo Yoshida, Tokyo (JP); Tsuyoshi Yoshida, Tokyo (JP); Yoshiaki Konishi, Tokyo (JP); and Kenji Ishii, Tokyo (JP)
Assigned to MITSUBISHI ELECTRIC CORPORATION, Tokyo (JP)
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
Filed on Oct. 23, 2023, as Appl. No. 18/492,547.
Application 18/492,547 is a division of application No. 17/899,719, filed on Aug. 31, 2022, granted, now 11,901,913.
Application 17/899,719 is a continuation of application No. PCT/JP2021/004798, filed on Feb. 9, 2021.
Claims priority of application No. PCT/JP2020/015223 (WO), filed on Apr. 2, 2020.
Prior Publication US 2024/0056099 A1, Feb. 15, 2024
Int. Cl. H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/1131 (2013.01) [H03M 13/611 (2013.01)] 7 Claims
OG exemplary drawing
 
1. An error correction coding apparatus to perform error correction coding using, as an error correction code sequence, a frame of m bits× n parallel symbols defining a multilevel symbol and input in m-bit parallel, where m and n are positive integers, the apparatus comprising:
an error correction coding circuit to perform error correction coding using, as information bits, m bits× n symbols including known bits of the frame assigned to a bit sequence specified in the error correction code sequence and generate error correction coded parity bits; and
a selector to replace the known bits of the error correction code sequence with the parity bits, wherein
the known bits in the frame of the error correction sequence have a bit state that is a coding target the bit state being recognized in advance by a transmission side and a reception side in common.