a processor;

a memory controller; and

a decoder, wherein the decoder receives a first codeword comprising first data and an associated first error correction code, the first error correction code comprising a first encoded plurality of bits comprising at least one metadata bit, and the decoder generates a first output corresponding to the at least one metadata bit having a first state and a second output corresponding to the at least one metadata bit having a second state,

wherein in response to determining that one of the first output or second output have a zero value, setting, by the decoder, a value of the at least one metadata bit to the first state or the second state corresponding to the first output or the second output having the zero value, and

in response to determining that both the first output and the second output are non-zero, decoding the first codeword corresponding to the at least one metadata bit having the first state and decoding the first codeword corresponding to the at least one metadata bit having the second state to determine a value of the at least one metadata bit.