US 12,261,621 B2
Successive approximation register (SAR) analog- to-digital converter (ADC) with input-dependent least significant bit (LSB) size
Behnam Sedighi, La Jolla, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 20, 2022, as Appl. No. 17/949,149.
Prior Publication US 2024/0097698 A1, Mar. 21, 2024
Int. Cl. H03M 1/46 (2006.01); H03M 1/18 (2006.01); H03M 1/36 (2006.01); H03M 1/08 (2006.01); H03M 1/12 (2006.01); H03M 1/38 (2006.01)
CPC H03M 1/462 (2013.01) [H03M 1/185 (2013.01); H03M 1/368 (2013.01); H03M 1/08 (2013.01); H03M 1/12 (2013.01); H03M 1/38 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal, wherein the SAR ADC is configured to output N bits, and wherein the SAR ADC is configured to convert the analog input signal to the digital output signal using less than N comparisons.