US 12,261,619 B2
Stochastic rounding switched capacitor computation cores useful for efficient deep learning inference
Chia-Yu Chen, Westchester, NY (US); Ankur Agrawal, Chappaqua, NY (US); Andrea Fasoli, San Jose, CA (US); and Kyu-hyoun Kim, Chappaqua, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 20, 2022, as Appl. No. 18/085,094.
Prior Publication US 2024/0204792 A1, Jun. 20, 2024
Int. Cl. H03M 1/38 (2006.01)
CPC H03M 1/38 (2013.01) 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
multiple analog to digital converters, wherein individual analog to digital converters are configured to produce a digital output from an analog input and configured to compute a least significant bit of the digital output by comparing an internal residual voltage for determination of the least significant bit and a residual voltage from another analog to digital converter.