US 12,261,613 B2
Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device
Vijayakrishna J. Vankayala, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 18, 2024, as Appl. No. 18/607,999.
Application 18/607,999 is a continuation of application No. 17/723,692, filed on Apr. 19, 2022, granted, now 11,955,981.
Prior Publication US 2024/0223196 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03L 7/191 (2006.01); G11C 7/10 (2006.01); H03K 19/20 (2006.01); H03L 7/197 (2006.01)
CPC H03L 7/191 (2013.01) [G11C 7/1039 (2013.01); H03K 19/20 (2013.01); H03L 7/1976 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first die, comprising:
a first plurality of memory cells; and
division circuitry configured to:
receive a clock;
generate a divided clock having a lower frequency than that of the clock; and
generate a plurality of component clocks from the divided clock; and
one or more transmitters configured to transmit the plurality of component clocks using a plurality of inter-die interconnects between the first die and a second die; and
the second die configured to receive and use the plurality of component clocks, wherein the first die is a primary memory die, and the second die is one of a plurality of die that are internal memory die that receive the plurality of component clocks from the primary memory die.