US 12,261,612 B2
Compact frequency-locked loop architecture for digital clocking
John Abcarius, San Diego, CA (US); Debesh Bhatta, San Diego, CA (US); Andrew Weil, San Diego, CA (US); Robert Martin Ondris, San Diego, CA (US); and Wenjing Yin, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 2, 2023, as Appl. No. 18/177,445.
Prior Publication US 2024/0297654 A1, Sep. 5, 2024
Int. Cl. H03L 7/099 (2006.01)
CPC H03L 7/0992 (2013.01) 29 Claims
OG exemplary drawing
 
1. A frequency-locked loop (FLL) circuit comprising:
an encoder;
a combiner comprising a first input coupled to an output of the encoder;
a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner;
a discrete-time integrator comprising an input coupled to an output of the DAC;
a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and
a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.