US 12,261,610 B2
Frequency locked loop circuit and clock signal generation method
Chin-Tung Chan, New Taipei (TW); Yan-Ting Wang, Hsinchu County (TW); Ren-Hong Luo, Hsinchu (TW); Chih-Wen Chen, Hsinchu County (TW); Hao-Che Hsu, Kaohsiung (TW); and Li-Wei Lin, Hsinchu (TW)
Assigned to NOVATEK Microelectronics Corp., Hsinchu (TW)
Filed by NOVATEK Microelectronics Corp., Hsinchu (TW)
Filed on Oct. 29, 2023, as Appl. No. 18/496,908.
Application 18/496,908 is a continuation in part of application No. 17/661,042, filed on Apr. 27, 2022, granted, now 11,881,865.
Application 17/661,042 is a continuation of application No. 16/727,882, filed on Dec. 26, 2019, granted, now 11,349,488, issued on May 31, 2022.
Prior Publication US 2024/0056086 A1, Feb. 15, 2024
Int. Cl. H03L 7/099 (2006.01); H03L 7/085 (2006.01); H03L 7/23 (2006.01)
CPC H03L 7/099 (2013.01) [H03L 7/085 (2013.01); H03L 7/23 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A frequency locked loop circuit, comprising:
an operational circuit comprising a positive terminal and a negative terminal, wherein the operational circuit is configured to output an operational signal according to a voltage difference between the positive terminal and the negative terminal;
a first impedance circuit electrically coupled to a first impedance node;
a second impedance circuit electrically coupled to a second impedance node;
a switching circuit electrically coupled to the first impedance node, the second impedance node, the positive terminal and the negative terminal, wherein the switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node; and
a frequency generation circuit electrically coupled to the operational circuit to receive the operational signal, and configured to periodically sample the operational signal to generate a sample signal to generate a clock signal, wherein an operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.