US 12,261,609 B1
Inter-PLL communication in a multi-PLL environment
Srinath Sridharan, Bangalore (IN); Ankit Seedher, Bangalore (IN); Raja Prabhu J, Bangalore (IN); Purva Choudhary, Bangalore (IN); Sandeep Sasi, Bangalore (IN); Akash Gupta, Bangalore (IN); Jeevabharathi G, Bangalore (IN); Bhupendra Sharma, Bangalore (IN); Debasish Behera, Bangalore (IN); Nandini Ganig BS, Bangalore (IN); and Chandrashekar BG, Bangalore (IN)
Assigned to Shaoxing Yuanfang Semiconductor Co., Ltd., Zhejiang (CN)
Filed by Shaoxing Yuanfang Semiconductor Co., Ltd., Shaoxing (CN)
Filed on Oct. 18, 2023, as Appl. No. 18/489,012.
Int. Cl. H03L 7/099 (2006.01); H03L 7/093 (2006.01)
CPC H03L 7/099 (2013.01) [H03L 7/093 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic block comprising:
a plurality of independent Phase-Locked Loops (PLLs), each PLL having an input path and an output path, wherein each independent PLL generates a corresponding output clock locked to a respective input clock; and
a switch matrix operable to concurrently connect a respective signal on the output path of each PLL to the input path of another PLL,
wherein each PLL comprises:
a phase detector and a low-pass filter, said low-pass filter operable to filter-out high-frequency components of an error signal generated by said phase detector and form a frequency-correction signal;
a frequency-correction signal combiner to combine said frequency-correction signal with one or more frequency-correction signals received from any of the other PLLs to form a combined signal; and
a controlled oscillator to generate said corresponding output clock of said PLL based on said combined signal,
wherein said respective signal is said frequency-correction signal of the corresponding PLL, wherein said frequency-correction signal is in the form of a digital value, and said switch matrix is a digital switch matrix.