CPC H03K 19/17728 (2013.01) [H03K 19/17736 (2013.01); H03K 19/17712 (2013.01)] | 19 Claims |
1. A System-on-Chip, comprising:
a data processing engine array comprising a plurality of data processing engines organized in a grid with each data processing engine including a stream switch, a core, and a memory module;
wherein each data processing engine is capable of conveying data to a different data processing engine via a first data path using the stream switch and via at least a second data path independent of the first data path in which the core accesses a memory module of an adjacent data processing engine via a memory interface, wherein the second data path circumvents the stream switch;
wherein the plurality of data processing engines are partitioned into at least a first partition and a second partition;
wherein the first partition includes one or more first data processing engines of the plurality of data processing engines;
wherein the second partition includes one or more second data processing engines of the plurality of data processing engines; and
wherein each partition is configured to implement an application that executes independently of the other partition.
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